Rapid Prototyping of Hardware Security Solutions
Rapid Prototyping of Hardware Security Solutions

The goal of the project is to design a high-throughput and low-power FPGA implementation of the newly proposed sparse FFT algorithm. For the purposes of guiding the implementation
effort, we had chosen the input data size as a million (220) points, with a maximum of 500 nonzero frequency coefficients. We had completed an initial implementation of the SFFT Core, which includes: 4096 point dense-FFT module, a top-511 element selector module, a Voting module and the Value-compute module. We have been improving the design performance and resource usage by modifying the pipeline of the design. We have also completed an extensive debugging of the design using customized test-benches. Given the filtered input data slices, our FPGAimplementation now produces the value-index pairs of the 500 most significant frequency components.

Principal Investigators
Arvind, CSAIL
Raymond Filippi, QCRI

Abhinav Agarwal, Haitham Hassanieh, Omid Abari, Ezz Hamed, Dina Katabi & Arvind, "High-Throughput Implementation of a Million-Point Sparse Fourier Transform," In Proceedings of the International Conference on Field Programmable Logic and applications (FPL), 2014