Rapid Prototyping of Hardware Security Solutions
Rapid Prototyping of Hardware Security Solutions

The goal of the project was to design a high-throughput and low-power FPGA implementation of the newly proposed sparse FFT algorithm. For the purposes of guiding the implementation
effort, the team chose the input data size as a million (220) points, with a maximum of 500 nonzero frequency coefficients. The team completed an initial implementation of the SFFT Core, which includes: 4096 point dense-FFT module, a top-511 element selector module, a Voting module and the Value-compute module. The team improved the design performance and resource usage by modifying the pipeline of the design. The researchers also completed an extensive debugging of the design using customized test-benches. Given the filtered input data slices, the project's FPGA implementation now produces the value-index pairs of the 500 most significant frequency components.

Principal Investigators
Arvind, CSAIL
Raymond Filippi, QCRI